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Flash D0 - 128kB PEROM

This upgrade is made as support for 4MB RAM extension, however can work without it. Target machines are Spectrum compatibile computers, but can be used in other constructions that use 16kB ROM.

  • Starts from ROM page 0.
  • Can support TR-DOS traps (TRETRAP).
  • Can support bit 4 of #7FFD port of ZX128 ROM switching.
  • Needs /CS to include /MREQ.
  • Can be disabled with /ROMCS=1 on edge slot.
  • Is dedicated for 29C010 memory.
  • 29C020 memory can be connected with a bit modified scheme (1 bit latch more and other powering solution, maybe next version with GAL).
  • Can work without the 4MB RAM extension - has simplified port decoder.
  • Can include ZXVGS with small romdisk (32kB to 64kB).
  • Can setup 4MB memory banks after a reset.

Bits 0..3 - ROM page

One of 16 ROM pages can be selected (with 29C020 PEROM). In case of 29C010, pages 0..7 are the same as 8..15. (When the 4MB RAM upgrade is present, there's no need for more ROM pages, as ROM can be simulated by write-protected RAM. But the RAM pages cannot support ZX128 ROM bankswitching nor TR-DOS traps.)

Bit 4 - write-protection

For better safety there's hardware PEROM write-protection. When bit 4 in #D0 is reset, PEROM is protected. When writing is enabled, any write will probably not damage the PEROM contents, but switches PEROM into poll mode, what result in compuer reset. To reprogram the PEROM, this bit must be set in page number.

Bit 5 - #7FFD switching

The line A14 (pin 27 in 28 pin socket) should be connected via 1kohm resistor to ouput of bit 4 latched in #7FFD port, when ZX128 compatibility circuit is present. This extra switching is active when bit 5 in #D0 is set and gives two ZX Spectrum 128K ROM banks.

Bit 6 - TR-DOS traps

The line A15 (pin 1 in 28 pin socket) should be connected via 1kohm resistor to /M1 of Z80CPU. This gives a possibility to emulate TR-DOS, as it has entry points in area of character set (#3D00..#3DFF), so switching with /M1 gives other data for normal reading and other for jumps in that area.

Bit 7 - ROM/RAM selection

Bit 7 enables PEROM when is set. This is for cooperation with 4MB RAM upgrade, where values #00..#7F select RAM page.

EXROM option

For use in Timex 2068, extra EXROM input option is designed. When this input is in low state, PEROM works as normal (as above). But pulling this input to high state switches the PEROM into EXROM mode. A16 of PEROM is foced into high state and features of bits 5 (ZX128) and 6 (TRETRAP) are disabled. In the EXROM mode, to pins 27 and 1 of the socket signals A14 and A15 of Z80 should be provided (in place of bit 4,#7FFD and /M1) by external multiplexer. This gives a 64kB ROM block in EXROM bank, build of pages 4..7 or 12..15.

The switching hardware

There are 8 latched outputs Q0..Q7, respectively to data bus D0..D7. The exception is Q3 that always latches 1, so later is called QH. QH is set with first port write and cleared with reset (/RES=0). The PEROM is disabled (with transistor) only when Q7=0 and QH=1.

After a reset all latches are set to 0. As Q7=0 the ROM should be disabled, but is not due to QH=0. The ROM bank 0 is selected. First value written to port #D0 should have the bit 7 set (#80..#FF). Next writes to #D0 port with bit 7 reset, disable the PEROM (and page in RAM when 4MB RAM extension is present).
Value OUTed to #D0 Lines of PEROM
A16 A15 A14
%0xxxxxxx /ROMCS=1 (PEROM is disabled)
%100xxCBA C B A
%101xxCBx C B A14 from socket
bit 4 of #7FFD port
%110xxCxA C A15 from socket
/M1
A
%111xxCxx C A15 from socket
/M1
A14 from socket
bit 4 of #7FFD port

The decoder needs to decode A0=0, A1=0, /WR=0 as they are not decoded in 4MB RAM upgrade and the selection line from 4MB RAM upgrade port decoder. When 4MB RAM upgrade is not present following confitions should be chcecked: A2=0, A3=0, A4=1, A5=0, A6=1, A7=1 and /IORQ=0.

In ZX Spectrum the ULA port access must be disabled while accessing #D0..#D3 ports (A2=0 or A5=0 should pull-up the /IOULA line).

Example (recommended) memory map

  • ROM0 has modified ZXROM code that is dedicated for interfaces that doesn't initialize #D0..#D3 ports. Just after reset it switches to ROM2.
  • ROM1 and ROM3 support the TR-DOS traps (TRETRAP). ROM1 is selected when opcode is fetched (/M1=0), ROM3 for data reading cycle (/M1=1). They have the same contents, except #3C00..#3FFF area, where in ROM1 are jump codes, while oridinary reading returns character set data from ROM3. ZXVGS entry points switch to code in ROM2.
  • ROM2 is the main ZXVGS code. This code uses some RAM pages to store variables. Can also test hardware or load ZXVGS code from harddisk into RAM.
  • ROM4 and ROM5 are free for romdisk files or another ROM set. (For 2068 mode, ROM4 can be filled with 8kB EXROM code and ROM5 can contain the 2068 HOME ROM.)
  • ROM6 and ROM7 allow the computer to work as ZX Spectrum 128kB (when ZX128 compatibility circuit is present).

first 64kB
A16=0
second 64kB
A16=1
bit 4 of #7FFD port /M1=0 /M1=1 A15=0 A15=1
0 ROM0
%10000000
ZXROM (boot)
ROM2
%10000010
ZXVGS code
ROM4
%10000100
(EXROM 2068)
ROM6
%10100110
ZX128 ROM0
1 ROM1
%11000001
TR-DOS traps
ROM3
%11000011
ZXROM (ZXVGS)
ROM5
%10000101
(HOME 2068)
ROM7
%10100111
ZX128 ROM1

External interface that uses hardware memory traps (+D, TI-of-TTL, etc.) and activates the 4MB RAM upgrade, should write #80 (128) into #D0 (208) port for ZX48 ROM or #A6 (166) for ZX128 ROM (so bit 4 in #7FFD port select the bank).

For better safety, the pages used should be tested if they contain correct contents. For example, the FlashD0 dedicated to Timex Sinclair 2068, can have 2068 ROM in ROM0 page, and pages ROM4..ROM7 can be used for extra EXROM code.

Present version

In present FlashD0 version (v004), A0, A1, A5, A6, /WR and /IORQ are decoded. The /IORQ input should be replaced by selection line from 4MB RAM extension decoder.

When FlashD0 is mounted together with Z80JOY, there's dimensions overlap. Z80JOY must be mounted in higher position (e.g. FlashD0 soldered directly to board, while Z80JOY in extra socket).

The version v003 upgraded to v004 compatibility is working without problems in Timex Computer 2048 (with TC2144 upgrade). The /CE signal is gated by /MREQ with NPN transistor (BC337).



Files for download

fd0prog.zip 1.8kB (2005-08-21 21:21)
FlashD0 simple programming code. Originally written by Pera Putnik and adapted for FlashD0 (29C010 only). Works, but should test bit 6, not 7.
FLD0-004.zip 29.3kB (2005-08-21 20:39)
Project v004 after prototipe test - Eagle data files.
FLD0-003.zip 25.3kB (2004-07-27 10:45)
(old) Prototipe project v003 - Eagle and Tango PCB data files.


Links to other pages

../../topic/t-98.html
[en] Description on the forum. FlashD0 upgrade dedicated for Timex 2068 computers. Second 64kB of PEROM is seen in EXROM.
http://members.tripod.com/~piters/zxfl_sch.htm
[en] Other idea for Flash by Pera Putnik - #A9 (169) port.

See also

ZX 4MB RAM upgrade
Upgrade to 4MB RAM for ZX Spectrum.
YABUS.TF
Two YABUS slots for Timex FDD 3000 with memory extension (4MB RAM).

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© 2005-12-01 15:04 Jarek Adamski, http://8bit.yarek.pl/