cpldfit: version J.40 Xilinx Inc. Fitter Report Design Name: ZXVGA Date: 1-30-2011, 9:18PM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 106/144 ( 74%) 298 /720 ( 41%) 192/432 ( 44%) 80 /144 ( 56%) 44 /81 ( 54%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 12/18 26/54 23/90 2/11 FB2 10/18 28/54 36/90 2/10 FB3 14/18 27/54 35/90 3/10 FB4 0/18 0/54 0/90 0/10 FB5 18/18* 28/54 45/90 3/10 FB6 18/18* 28/54 74/90 9/10 FB7 16/18 27/54 35/90 8/10 FB8 18/18* 28/54 50/90 10/10* ----- ----- ----- ----- 106/144 192/432 298/720 37/81 * - Resource is exhausted ** Global Control Resources ** Signal 'VGA_CLK' mapped onto global clock net GCK1. Signal 'ZX_CLK' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 5 5 | I/O : 42 73 Output : 29 29 | GCK/IO : 2 3 Bidirectional : 8 8 | GTS/IO : 0 4 GCK : 2 2 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 44 44 ** Power Data ** There are 106 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<10>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<11>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<12>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<13>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<14>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<15>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<8>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'RAM_DT<9>'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 37 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State VGA_IG1 2 6 FB1_2 11 I/O O STD FAST VGA_IG2 2 6 FB1_3 12 I/O O STD FAST VGA_IR1 2 6 FB2_15 9 I/O O STD FAST VGA_IR2 2 6 FB2_17 10 I/O O STD FAST VGA_R 2 4 FB3_14 32 I/O O STD FAST VGA_G 2 4 FB3_15 33 I/O O STD FAST VGA_B 2 4 FB3_17 34 I/O O STD FAST VGA_IB 2 6 FB5_2 35 I/O O STD FAST VGA_HS 2 12 FB5_5 36 I/O O STD FAST RESET VGA_VS 3 12 FB5_6 37 I/O O STD FAST RESET RAM_AD<9> 3 4 FB6_2 74 I/O O STD FAST RAM_DT<6> 5 9 FB6_5 76 I/O I/O STD FAST RESET RAM_DT<7> 5 9 FB6_6 77 I/O I/O STD FAST RESET RAM_DT<5> 5 9 FB6_8 78 I/O I/O STD FAST RESET RAM_DT<4> 5 9 FB6_9 79 I/O I/O STD FAST RESET RAM_DT<3> 5 9 FB6_11 80 I/O I/O STD FAST RESET RAM_DT<2> 5 9 FB6_12 81 I/O I/O STD FAST RESET RAM_DT<1> 5 9 FB6_14 82 I/O I/O STD FAST RESET RAM_DT<0> 5 9 FB6_15 85 I/O I/O STD FAST RESET RAM_AD<10> 3 4 FB7_6 53 I/O O STD FAST RAM_AD<11> 3 4 FB7_8 54 I/O O STD FAST RAM_AD<12> 3 4 FB7_9 55 I/O O STD FAST RAM_AD<13> 3 4 FB7_11 56 I/O O STD FAST RAM_AD<14> 3 4 FB7_12 58 I/O O STD FAST RAM_AD<15> 3 4 FB7_14 59 I/O O STD FAST RAM_AD<17> 0 0 FB7_15 60 I/O O STD FAST RAM_AD<16> 3 4 FB7_17 61 I/O O STD FAST RAM_AD<0> 3 4 FB8_2 63 I/O O STD FAST RAM_AD<1> 3 4 FB8_5 64 I/O O STD FAST RAM_AD<2> 3 4 FB8_6 65 I/O O STD FAST RAM_AD<3> 3 4 FB8_8 66 I/O O STD FAST RAM_AD<4> 3 4 FB8_9 67 I/O O STD FAST RAM_WR 5 7 FB8_11 68 I/O O STD FAST RESET RAM_AD<5> 3 4 FB8_12 70 I/O O STD FAST RAM_AD<6> 3 4 FB8_14 71 I/O O STD FAST RAM_AD<7> 3 4 FB8_15 72 I/O O STD FAST RAM_AD<8> 3 4 FB8_17 73 I/O O STD FAST ** 69 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State zxPAGE 1 11 FB1_9 STD RESET zxCTCV<8> 2 20 FB1_10 STD RESET zxCTCV<7> 2 19 FB1_11 STD RESET zxCTCV<6> 2 18 FB1_12 STD RESET zxCTCV<5> 2 17 FB1_13 STD RESET zxCTCV<4> 2 16 FB1_14 STD RESET zxCTCV<3> 2 15 FB1_15 STD RESET zxCTCV<2> 2 14 FB1_16 STD RESET zxCTCV<1> 2 13 FB1_17 STD RESET zxCTCV<0> 2 12 FB1_18 STD RESET zxADR<7> 4 8 FB2_9 STD RESET zxADR<6> 4 8 FB2_10 STD RESET zxADR<5> 4 8 FB2_11 STD RESET zxADR<4> 4 8 FB2_12 STD RESET zxADR<3> 4 8 FB2_13 STD RESET zxADR<2> 4 8 FB2_14 STD RESET zxADR<1> 4 8 FB2_16 STD RESET zxADR<0> 4 8 FB2_18 STD RESET rWRREQ 2 2 FB3_5 STD RESET rPIXEL<5> 2 4 FB3_6 STD RESET rPIXEL<4> 2 4 FB3_7 STD RESET rPIXEL<3> 2 4 FB3_8 STD RESET zxCTCH<8> 3 14 FB3_9 STD RESET zxCTCH<7> 3 13 FB3_10 STD RESET zxCTCH<6> 3 12 FB3_11 STD RESET zxCTCH<5> 3 11 FB3_12 STD RESET zxCTCH<4> 3 10 FB3_13 STD RESET zxCTCH<3> 3 9 FB3_16 STD RESET zxCTCH<2> 3 8 FB3_18 STD RESET vgaCTCV<8> 2 19 FB5_1 STD RESET vgaCTCV<7> 2 18 FB5_3 STD RESET vgaCTCV<6> 2 17 FB5_4 STD RESET vgaCTCV<5> 2 16 FB5_7 STD RESET vgaCTCV<4> 2 15 FB5_8 STD RESET vgaCTCV<1> 2 12 FB5_9 STD RESET vgaCTCV<0> 2 21 FB5_10 STD RESET vgaCTCV<9> 3 21 FB5_11 STD RESET vgaCTCV<3> 3 21 FB5_12 STD RESET vgaCTCV<2> 3 21 FB5_13 STD RESET vgaCTCH<8> 3 11 FB5_14 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State vgaCTCH<4> 3 11 FB5_15 STD RESET vgaCTCH<3> 3 11 FB5_16 STD RESET vgaCTCH<2> 3 11 FB5_17 STD RESET vgaCTCH<1> 3 11 FB5_18 STD RESET zxDIV5<0> 2 5 FB6_1 STD RESET zxDIV5<1> 3 4 FB6_3 STD RESET zxCTCH<1> 3 7 FB6_4 STD RESET zxCTCH<0> 3 6 FB6_7 STD RESET zxDIV5<2> 4 5 FB6_10 STD RESET rZXDT4<3> 4 8 FB6_13 STD RESET rZXDT4<2> 4 8 FB6_16 STD RESET rZXDT4<1> 4 8 FB6_17 STD RESET rZXDT4<0> 4 8 FB6_18 STD RESET vgaDIV 0 0 FB7_3 STD RESET rZX_CSYC 1 1 FB7_4 STD RESET vgaPAGE 2 12 FB7_5 STD RESET rPIXEL<7> 2 4 FB7_7 STD RESET rPIXEL<6> 2 4 FB7_10 STD RESET rPIXEL<2> 2 4 FB7_13 STD RESET rPIXEL<1> 2 4 FB7_16 STD RESET vgaENv 3 12 FB7_18 STD RESET vgaENA 2 13 FB8_1 STD RESET vgaCTCH<7> 2 8 FB8_3 STD RESET vgaCTCH<6> 2 7 FB8_4 STD RESET vgaCTCH<5> 2 6 FB8_7 STD RESET vgaCTCH<0> 2 11 FB8_10 STD RESET rPIXEL<0> 2 4 FB8_13 STD RESET vgaCTCH<9> 3 11 FB8_16 STD RESET pWRREQ 3 7 FB8_18 STD RESET ** 7 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use ZX_RGBI<3> FB1_5 13 I/O I ZX_CSYC FB1_6 14 I/O I VGA_CLK FB1_17 22 GCK/I/O GCK ZX_RGBI<0> FB2_11 6 I/O I ZX_RGBI<1> FB2_12 7 I/O I ZX_RGBI<2> FB2_14 8 I/O I ZX_CLK FB3_2 23 GCK/I/O GCK Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 26/28 Number of signals used by logic mapping into function block: 26 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) VGA_IG1 2 0 0 3 FB1_2 11 I/O O VGA_IG2 2 0 0 3 FB1_3 12 I/O O (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 13 I/O I (unused) 0 0 0 5 FB1_6 14 I/O I (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 15 I/O zxPAGE 1 0 0 4 FB1_9 16 I/O (b) zxCTCV<8> 2 0 0 3 FB1_10 (b) (b) zxCTCV<7> 2 0 0 3 FB1_11 17 I/O (b) zxCTCV<6> 2 0 0 3 FB1_12 18 I/O (b) zxCTCV<5> 2 0 0 3 FB1_13 (b) (b) zxCTCV<4> 2 0 0 3 FB1_14 19 I/O (b) zxCTCV<3> 2 0 0 3 FB1_15 20 I/O (b) zxCTCV<2> 2 0 0 3 FB1_16 (b) (b) zxCTCV<1> 2 0 0 3 FB1_17 22 GCK/I/O GCK zxCTCV<0> 2 0 0 3 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: ZX_CSYC 10: zxCTCH<1> 19: zxCTCV<1> 2: rPIXEL<1> 11: zxCTCH<2> 20: zxCTCV<2> 3: rPIXEL<3> 12: zxCTCH<3> 21: zxCTCV<3> 4: rPIXEL<5> 13: zxCTCH<4> 22: zxCTCV<4> 5: rPIXEL<7> 14: zxCTCH<5> 23: zxCTCV<5> 6: rZX_CSYC 15: zxCTCH<6> 24: zxCTCV<6> 7: vgaCTCH<1> 16: zxCTCH<7> 25: zxCTCV<7> 8: vgaENA 17: zxCTCH<8> 26: zxCTCV<8> 9: zxCTCH<0> 18: zxCTCV<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs VGA_IG1 .XXXX.XX................................ 6 VGA_IG2 .XXXX.XX................................ 6 zxPAGE X....X...........XXXXXXXXX.............. 11 zxCTCV<8> X....X..XXXXXXXXXXXXXXXXXX.............. 20 zxCTCV<7> X....X..XXXXXXXXXXXXXXXXX............... 19 zxCTCV<6> X....X..XXXXXXXXXXXXXXXX................ 18 zxCTCV<5> X....X..XXXXXXXXXXXXXXX................. 17 zxCTCV<4> X....X..XXXXXXXXXXXXXX.................. 16 zxCTCV<3> X....X..XXXXXXXXXXXXX................... 15 zxCTCV<2> X....X..XXXXXXXXXXXX.................... 14 zxCTCV<1> X....X..XXXXXXXXXXX..................... 13 zxCTCV<0> X....X..XXXXXXXXXX...................... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 99 GSR/I/O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 1 GTS/I/O (unused) 0 0 0 5 FB2_6 2 GTS/I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 3 GTS/I/O zxADR<7> 4 0 0 1 FB2_9 4 GTS/I/O (b) zxADR<6> 4 0 0 1 FB2_10 (b) (b) zxADR<5> 4 0 0 1 FB2_11 6 I/O I zxADR<4> 4 0 0 1 FB2_12 7 I/O I zxADR<3> 4 0 0 1 FB2_13 (b) (b) zxADR<2> 4 0 0 1 FB2_14 8 I/O I VGA_IR1 2 0 0 3 FB2_15 9 I/O O zxADR<1> 4 0 0 1 FB2_16 (b) (b) VGA_IR2 2 0 0 3 FB2_17 10 I/O O zxADR<0> 4 0 0 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: ZX_CSYC 11: zxADR<2> 20: zxCTCH<3> 2: rPIXEL<0> 12: zxADR<3> 21: zxCTCH<4> 3: rPIXEL<3> 13: zxADR<4> 22: zxCTCH<5> 4: rPIXEL<4> 14: zxADR<5> 23: zxCTCH<6> 5: rPIXEL<7> 15: zxADR<6> 24: zxCTCH<7> 6: rZX_CSYC 16: zxADR<7> 25: zxCTCH<8> 7: vgaCTCH<1> 17: zxCTCH<0> 26: zxDIV5<0> 8: vgaENA 18: zxCTCH<1> 27: zxDIV5<1> 9: zxADR<0> 19: zxCTCH<2> 28: zxDIV5<2> 10: zxADR<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs zxADR<7> X....X.........XX.......XXXX............ 8 zxADR<6> X....X........X.X......X.XXX............ 8 zxADR<5> X....X.......X..X.....X..XXX............ 8 zxADR<4> X....X......X...X....X...XXX............ 8 zxADR<3> X....X.....X....X...X....XXX............ 8 zxADR<2> X....X....X.....X..X.....XXX............ 8 VGA_IR1 .XXXX.XX................................ 6 zxADR<1> X....X...X......X.X......XXX............ 8 VGA_IR2 .XXXX.XX................................ 6 zxADR<0> X....X..X.......XX.......XXX............ 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 27/27 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 23 GCK/I/O GCK (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) rWRREQ 2 0 0 3 FB3_5 24 I/O (b) rPIXEL<5> 2 0 0 3 FB3_6 25 I/O (b) rPIXEL<4> 2 0 0 3 FB3_7 (b) (b) rPIXEL<3> 2 0 0 3 FB3_8 27 GCK/I/O (b) zxCTCH<8> 3 0 0 2 FB3_9 28 I/O (b) zxCTCH<7> 3 0 0 2 FB3_10 (b) (b) zxCTCH<6> 3 0 0 2 FB3_11 29 I/O (b) zxCTCH<5> 3 0 0 2 FB3_12 30 I/O (b) zxCTCH<4> 3 0 0 2 FB3_13 (b) (b) VGA_R 2 0 0 3 FB3_14 32 I/O O VGA_G 2 0 0 3 FB3_15 33 I/O O zxCTCH<3> 3 0 0 2 FB3_16 (b) (b) VGA_B 2 0 0 3 FB3_17 34 I/O O zxCTCH<2> 3 0 0 2 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: RAM_DT<3>.PIN 10: rPIXEL<6> 19: zxCTCH<3> 2: RAM_DT<4>.PIN 11: rZX_CSYC 20: zxCTCH<4> 3: RAM_DT<5>.PIN 12: vgaCTCH<0> 21: zxCTCH<5> 4: ZX_CSYC 13: vgaCTCH<1> 22: zxCTCH<6> 5: rPIXEL<0> 14: vgaDIV 23: zxCTCH<7> 6: rPIXEL<1> 15: vgaENA 24: zxCTCH<8> 7: rPIXEL<2> 16: zxCTCH<0> 25: zxDIV5<0> 8: rPIXEL<4> 17: zxCTCH<1> 26: zxDIV5<1> 9: rPIXEL<5> 18: zxCTCH<2> 27: zxDIV5<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs rWRREQ .............X.X........................ 2 rPIXEL<5> ..X........XXX.......................... 4 rPIXEL<4> .X.........XXX.......................... 4 rPIXEL<3> X..........XXX.......................... 4 zxCTCH<8> ...X......X....XXXXXXXXXXXX............. 14 zxCTCH<7> ...X......X....XXXXXXXX.XXX............. 13 zxCTCH<6> ...X......X....XXXXXXX..XXX............. 12 zxCTCH<5> ...X......X....XXXXXX...XXX............. 11 zxCTCH<4> ...X......X....XXXXX....XXX............. 10 VGA_R ....X..X....X.X......................... 4 VGA_G .....X..X...X.X......................... 4 zxCTCH<3> ...X......X....XXXX.....XXX............. 9 VGA_B ......X..X..X.X......................... 4 zxCTCH<2> ...X......X....XXX......XXX............. 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 87 I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 89 I/O (unused) 0 0 0 5 FB4_6 90 I/O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 91 I/O (unused) 0 0 0 5 FB4_9 92 I/O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 93 I/O (unused) 0 0 0 5 FB4_12 94 I/O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 95 I/O (unused) 0 0 0 5 FB4_15 96 I/O (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 97 I/O (unused) 0 0 0 5 FB4_18 (b) *********************************** FB5 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use vgaCTCV<8> 2 0 0 3 FB5_1 (b) (b) VGA_IB 2 0 0 3 FB5_2 35 I/O O vgaCTCV<7> 2 0 0 3 FB5_3 (b) (b) vgaCTCV<6> 2 0 0 3 FB5_4 (b) (b) VGA_HS 2 0 0 3 FB5_5 36 I/O O VGA_VS 3 0 0 2 FB5_6 37 I/O O vgaCTCV<5> 2 0 0 3 FB5_7 (b) (b) vgaCTCV<4> 2 0 0 3 FB5_8 39 I/O (b) vgaCTCV<1> 2 0 0 3 FB5_9 40 I/O (b) vgaCTCV<0> 2 0 0 3 FB5_10 (b) (b) vgaCTCV<9> 3 0 0 2 FB5_11 41 I/O (b) vgaCTCV<3> 3 0 0 2 FB5_12 42 I/O (b) vgaCTCV<2> 3 0 0 2 FB5_13 (b) (b) vgaCTCH<8> 3 0 0 2 FB5_14 43 I/O (b) vgaCTCH<4> 3 0 0 2 FB5_15 46 I/O (b) vgaCTCH<3> 3 0 0 2 FB5_16 (b) (b) vgaCTCH<2> 3 0 0 2 FB5_17 49 I/O (b) vgaCTCH<1> 3 0 0 2 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: VGA_HS 11: vgaCTCH<4> 20: vgaCTCV<3> 2: VGA_VS 12: vgaCTCH<5> 21: vgaCTCV<4> 3: rPIXEL<2> 13: vgaCTCH<6> 22: vgaCTCV<5> 4: rPIXEL<3> 14: vgaCTCH<7> 23: vgaCTCV<6> 5: rPIXEL<6> 15: vgaCTCH<8> 24: vgaCTCV<7> 6: rPIXEL<7> 16: vgaCTCH<9> 25: vgaCTCV<8> 7: vgaCTCH<0> 17: vgaCTCV<0> 26: vgaCTCV<9> 8: vgaCTCH<1> 18: vgaCTCV<1> 27: vgaDIV 9: vgaCTCH<2> 19: vgaCTCV<2> 28: vgaENA 10: vgaCTCH<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs vgaCTCV<8> ......XXXXXXXXXXXXXXXXXX..X............. 19 VGA_IB ..XXXX.X...................X............ 6 vgaCTCV<7> ......XXXXXXXXXXXXXXXXX...X............. 18 vgaCTCV<6> ......XXXXXXXXXXXXXXXX....X............. 17 VGA_HS X.....XXXXXXXXXX..........X............. 12 VGA_VS .X..............XXXXXXXXXXX............. 12 vgaCTCV<5> ......XXXXXXXXXXXXXXX.....X............. 16 vgaCTCV<4> ......XXXXXXXXXXXXXX......X............. 15 vgaCTCV<1> ......XXXXXXXXXXX.........X............. 12 vgaCTCV<0> ......XXXXXXXXXXXXXXXXXXXXX............. 21 vgaCTCV<9> ......XXXXXXXXXXXXXXXXXXXXX............. 21 vgaCTCV<3> ......XXXXXXXXXXXXXXXXXXXXX............. 21 vgaCTCV<2> ......XXXXXXXXXXXXXXXXXXXXX............. 21 vgaCTCH<8> ......XXXXXXXXXX..........X............. 11 vgaCTCH<4> ......XXXXXXXXXX..........X............. 11 vgaCTCH<3> ......XXXXXXXXXX..........X............. 11 vgaCTCH<2> ......XXXXXXXXXX..........X............. 11 vgaCTCH<1> ......XXXXXXXXXX..........X............. 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use zxDIV5<0> 2 0 0 3 FB6_1 (b) (b) RAM_AD<9> 3 0 0 2 FB6_2 74 I/O O zxDIV5<1> 3 0 0 2 FB6_3 (b) (b) zxCTCH<1> 3 0 0 2 FB6_4 (b) (b) RAM_DT<6> 5 0 0 0 FB6_5 76 I/O I/O RAM_DT<7> 5 0 0 0 FB6_6 77 I/O I/O zxCTCH<0> 3 0 0 2 FB6_7 (b) (b) RAM_DT<5> 5 0 0 0 FB6_8 78 I/O I/O RAM_DT<4> 5 0 0 0 FB6_9 79 I/O I/O zxDIV5<2> 4 0 0 1 FB6_10 (b) (b) RAM_DT<3> 5 0 0 0 FB6_11 80 I/O I/O RAM_DT<2> 5 0 0 0 FB6_12 81 I/O I/O rZXDT4<3> 4 0 0 1 FB6_13 (b) (b) RAM_DT<1> 5 0 0 0 FB6_14 82 I/O I/O RAM_DT<0> 5 0 0 0 FB6_15 85 I/O I/O rZXDT4<2> 4 0 0 1 FB6_16 (b) (b) rZXDT4<1> 4 0 0 1 FB6_17 86 I/O (b) rZXDT4<0> 4 0 0 1 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: RAM_DT<0> 11: ZX_RGBI<0> 20: vgaCTCH<0> 2: RAM_DT<1> 12: ZX_RGBI<1> 21: vgaCTCH<1> 3: RAM_DT<2> 13: ZX_RGBI<2> 22: vgaCTCV<2> 4: RAM_DT<3> 14: ZX_RGBI<3> 23: zxCTCH<0> 5: RAM_DT<4> 15: rZXDT4<0> 24: zxCTCH<1> 6: RAM_DT<5> 16: rZXDT4<1> 25: zxCTCV<1> 7: RAM_DT<6> 17: rZXDT4<2> 26: zxDIV5<0> 8: RAM_DT<7> 18: rZXDT4<3> 27: zxDIV5<1> 9: RAM_WR 19: rZX_CSYC 28: zxDIV5<2> 10: ZX_CSYC Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs zxDIV5<0> .........X........X......XXX............ 5 RAM_AD<9> ...................XXX..X............... 4 zxDIV5<1> .........X........X......XX............. 4 zxCTCH<1> .........X........X...XX.XXX............ 7 RAM_DT<6> ......X.XX..X.....X...X..XXX............ 9 RAM_DT<7> .......XXX...X....X...X..XXX............ 9 zxCTCH<0> .........X........X...X..XXX............ 6 RAM_DT<5> .....X..XX.X......X...X..XXX............ 9 RAM_DT<4> ....X...XXX.......X...X..XXX............ 9 zxDIV5<2> .........X........X......XXX............ 5 RAM_DT<3> ...X....XX.......XX...X..XXX............ 9 RAM_DT<2> ..X.....XX......X.X...X..XXX............ 9 rZXDT4<3> .........X...X...XX...X..XXX............ 8 RAM_DT<1> .X......XX.....X..X...X..XXX............ 9 RAM_DT<0> X.......XX....X...X...X..XXX............ 9 rZXDT4<2> .........X..X...X.X...X..XXX............ 8 rZXDT4<1> .........X.X...X..X...X..XXX............ 8 rZXDT4<0> .........XX...X...X...X..XXX............ 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 27/27 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB7_1 (b) (unused) 0 0 0 5 FB7_2 50 I/O vgaDIV 0 0 0 5 FB7_3 (b) (b) rZX_CSYC 1 0 0 4 FB7_4 (b) (b) vgaPAGE 2 0 0 3 FB7_5 52 I/O (b) RAM_AD<10> 3 0 0 2 FB7_6 53 I/O O rPIXEL<7> 2 0 0 3 FB7_7 (b) (b) RAM_AD<11> 3 0 0 2 FB7_8 54 I/O O RAM_AD<12> 3 0 0 2 FB7_9 55 I/O O rPIXEL<6> 2 0 0 3 FB7_10 (b) (b) RAM_AD<13> 3 0 0 2 FB7_11 56 I/O O RAM_AD<14> 3 0 0 2 FB7_12 58 I/O O rPIXEL<2> 2 0 0 3 FB7_13 (b) (b) RAM_AD<15> 3 0 0 2 FB7_14 59 I/O O RAM_AD<17> 0 0 0 5 FB7_15 60 I/O O rPIXEL<1> 2 0 0 3 FB7_16 (b) (b) RAM_AD<16> 3 0 0 2 FB7_17 61 I/O O vgaENv 3 0 0 2 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: RAM_DT<1>.PIN 10: vgaCTCV<2> 19: vgaENv 2: RAM_DT<2>.PIN 11: vgaCTCV<3> 20: vgaPAGE 3: RAM_DT<6>.PIN 12: vgaCTCV<4> 21: zxCTCV<2> 4: RAM_DT<7>.PIN 13: vgaCTCV<5> 22: zxCTCV<3> 5: ZX_CSYC 14: vgaCTCV<6> 23: zxCTCV<4> 6: vgaCTCH<0> 15: vgaCTCV<7> 24: zxCTCV<5> 7: vgaCTCH<1> 16: vgaCTCV<8> 25: zxCTCV<6> 8: vgaCTCV<0> 17: vgaCTCV<9> 26: zxCTCV<7> 9: vgaCTCV<1> 18: vgaDIV 27: zxPAGE Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs vgaDIV ........................................ 0 rZX_CSYC ....X................................... 1 vgaPAGE .......XXXXXXXXXXX........X............. 12 RAM_AD<10> .....XX...X.........X................... 4 rPIXEL<7> ...X.XX..........X...................... 4 RAM_AD<11> .....XX....X.........X.................. 4 RAM_AD<12> .....XX.....X.........X................. 4 rPIXEL<6> ..X..XX..........X...................... 4 RAM_AD<13> .....XX......X.........X................ 4 RAM_AD<14> .....XX.......X.........X............... 4 rPIXEL<2> .X...XX..........X...................... 4 RAM_AD<15> .....XX........X.........X.............. 4 RAM_AD<17> ........................................ 0 rPIXEL<1> X....XX..........X...................... 4 RAM_AD<16> .....XX............X......X............. 4 vgaENv .......XXXXXXXXXXXX..................... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use vgaENA 2 0 0 3 FB8_1 (b) (b) RAM_AD<0> 3 0 0 2 FB8_2 63 I/O O vgaCTCH<7> 2 0 0 3 FB8_3 (b) (b) vgaCTCH<6> 2 0 0 3 FB8_4 (b) (b) RAM_AD<1> 3 0 0 2 FB8_5 64 I/O O RAM_AD<2> 3 0 0 2 FB8_6 65 I/O O vgaCTCH<5> 2 0 0 3 FB8_7 (b) (b) RAM_AD<3> 3 0 0 2 FB8_8 66 I/O O RAM_AD<4> 3 0 0 2 FB8_9 67 I/O O vgaCTCH<0> 2 0 0 3 FB8_10 (b) (b) RAM_WR 5 0 0 0 FB8_11 68 I/O O RAM_AD<5> 3 0 0 2 FB8_12 70 I/O O rPIXEL<0> 2 0 0 3 FB8_13 (b) (b) RAM_AD<6> 3 0 0 2 FB8_14 71 I/O O RAM_AD<7> 3 0 0 2 FB8_15 72 I/O O vgaCTCH<9> 3 0 0 2 FB8_16 (b) (b) RAM_AD<8> 3 0 0 2 FB8_17 73 I/O O pWRREQ 3 0 0 2 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: RAM_DT<0>.PIN 11: vgaCTCH<7> 20: zxADR<2> 2: pWRREQ 12: vgaCTCH<8> 21: zxADR<3> 3: rWRREQ 13: vgaCTCH<9> 22: zxADR<4> 4: vgaCTCH<0> 14: vgaCTCV<1> 23: zxADR<5> 5: vgaCTCH<1> 15: vgaDIV 24: zxADR<6> 6: vgaCTCH<2> 16: vgaENA 25: zxADR<7> 7: vgaCTCH<3> 17: vgaENv 26: zxCTCH<0> 8: vgaCTCH<4> 18: zxADR<0> 27: zxCTCV<0> 9: vgaCTCH<5> 19: zxADR<1> 28: zxCTCV<8> 10: vgaCTCH<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs vgaENA ...XXXXXXXXXX.XXX....................... 13 RAM_AD<0> ...XXX...........X...................... 4 vgaCTCH<7> ...XXXXXXX....X......................... 8 vgaCTCH<6> ...XXXXXX.....X......................... 7 RAM_AD<1> ...XX.X...........X..................... 4 RAM_AD<2> ...XX..X...........X.................... 4 vgaCTCH<5> ...XXXXX......X......................... 6 RAM_AD<3> ...XX...X...........X................... 4 RAM_AD<4> ...XX....X...........X.................. 4 vgaCTCH<0> ...XXXXXXXXXX.X......................... 11 RAM_WR .XXXX.........X..........X.X............ 7 RAM_AD<5> ...XX.....X...........X................. 4 rPIXEL<0> X..XX.........X......................... 4 RAM_AD<6> ...XX......X...........X................ 4 RAM_AD<7> ...XX.......X...........X............... 4 vgaCTCH<9> ...XXXXXXXXXX.X......................... 11 RAM_AD<8> ...XX........X............X............. 4 pWRREQ .XXXX.........X..........X.X............ 7 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** RAM_AD(0) <= ((NOT vgaCTCH(1) AND zxADR(0)) OR (NOT vgaCTCH(0) AND zxADR(0)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(2))); RAM_AD(1) <= ((NOT vgaCTCH(1) AND zxADR(1)) OR (NOT vgaCTCH(0) AND zxADR(1)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(3))); RAM_AD(2) <= ((NOT vgaCTCH(1) AND zxADR(2)) OR (NOT vgaCTCH(0) AND zxADR(2)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4))); RAM_AD(3) <= ((NOT vgaCTCH(1) AND zxADR(3)) OR (NOT vgaCTCH(0) AND zxADR(3)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(5))); RAM_AD(4) <= ((NOT vgaCTCH(1) AND zxADR(4)) OR (NOT vgaCTCH(0) AND zxADR(4)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(6))); RAM_AD(5) <= ((NOT vgaCTCH(1) AND zxADR(5)) OR (NOT vgaCTCH(0) AND zxADR(5)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(7))); RAM_AD(6) <= ((NOT vgaCTCH(1) AND zxADR(6)) OR (NOT vgaCTCH(0) AND zxADR(6)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(8))); RAM_AD(7) <= ((NOT vgaCTCH(1) AND zxADR(7)) OR (NOT vgaCTCH(0) AND zxADR(7)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(9))); RAM_AD(8) <= ((NOT vgaCTCH(1) AND zxCTCV(0)) OR (NOT vgaCTCH(0) AND zxCTCV(0)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(1))); RAM_AD(9) <= ((NOT vgaCTCH(1) AND zxCTCV(1)) OR (NOT vgaCTCH(0) AND zxCTCV(1)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(2))); RAM_AD(10) <= ((NOT vgaCTCH(1) AND zxCTCV(2)) OR (NOT vgaCTCH(0) AND zxCTCV(2)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(3))); RAM_AD(11) <= ((NOT vgaCTCH(1) AND zxCTCV(3)) OR (NOT vgaCTCH(0) AND zxCTCV(3)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(4))); RAM_AD(12) <= ((NOT vgaCTCH(1) AND zxCTCV(4)) OR (NOT vgaCTCH(0) AND zxCTCV(4)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(5))); RAM_AD(13) <= ((NOT vgaCTCH(1) AND zxCTCV(5)) OR (NOT vgaCTCH(0) AND zxCTCV(5)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(6))); RAM_AD(14) <= ((NOT vgaCTCH(1) AND zxCTCV(6)) OR (NOT vgaCTCH(0) AND zxCTCV(6)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(7))); RAM_AD(15) <= ((NOT vgaCTCH(1) AND zxCTCV(7)) OR (NOT vgaCTCH(0) AND zxCTCV(7)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(8))); RAM_AD(16) <= ((NOT vgaCTCH(1) AND zxPAGE) OR (NOT vgaCTCH(0) AND zxPAGE) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaPAGE)); RAM_AD(17) <= '0'; FTCPE_RAM_DT0: FTCPE port map (RAM_DT_I(0),RAM_DT_T(0),NOT ZX_CLK,'0','0'); RAM_DT_T(0) <= ((RAM_DT(0) AND zxCTCH(0) AND NOT rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(0) AND zxCTCH(0) AND NOT rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(0) AND zxCTCH(0) AND rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(0) AND zxCTCH(0) AND rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(0) <= RAM_DT_I(0) when RAM_DT_OE(0) = '1' else 'Z'; RAM_DT_OE(0) <= NOT RAM_WR; FTCPE_RAM_DT1: FTCPE port map (RAM_DT_I(1),RAM_DT_T(1),NOT ZX_CLK,'0','0'); RAM_DT_T(1) <= ((RAM_DT(1) AND zxCTCH(0) AND NOT rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(1) AND zxCTCH(0) AND NOT rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(1) AND zxCTCH(0) AND rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(1) AND zxCTCH(0) AND rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(1) <= RAM_DT_I(1) when RAM_DT_OE(1) = '1' else 'Z'; RAM_DT_OE(1) <= NOT RAM_WR; FTCPE_RAM_DT2: FTCPE port map (RAM_DT_I(2),RAM_DT_T(2),NOT ZX_CLK,'0','0'); RAM_DT_T(2) <= ((RAM_DT(2) AND zxCTCH(0) AND NOT rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(2) AND zxCTCH(0) AND NOT rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(2) AND zxCTCH(0) AND rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(2) AND zxCTCH(0) AND rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(2) <= RAM_DT_I(2) when RAM_DT_OE(2) = '1' else 'Z'; RAM_DT_OE(2) <= NOT RAM_WR; FTCPE_RAM_DT3: FTCPE port map (RAM_DT_I(3),RAM_DT_T(3),NOT ZX_CLK,'0','0'); RAM_DT_T(3) <= ((RAM_DT(3) AND zxCTCH(0) AND NOT rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(3) AND zxCTCH(0) AND NOT rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(3) AND zxCTCH(0) AND rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(3) AND zxCTCH(0) AND rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(3) <= RAM_DT_I(3) when RAM_DT_OE(3) = '1' else 'Z'; RAM_DT_OE(3) <= NOT RAM_WR; FTCPE_RAM_DT4: FTCPE port map (RAM_DT_I(4),RAM_DT_T(4),NOT ZX_CLK,'0','0'); RAM_DT_T(4) <= ((ZX_RGBI(0) AND NOT RAM_DT(4) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(0) AND NOT RAM_DT(4) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND RAM_DT(4) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND RAM_DT(4) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(4) <= RAM_DT_I(4) when RAM_DT_OE(4) = '1' else 'Z'; RAM_DT_OE(4) <= NOT RAM_WR; FTCPE_RAM_DT5: FTCPE port map (RAM_DT_I(5),RAM_DT_T(5),NOT ZX_CLK,'0','0'); RAM_DT_T(5) <= ((ZX_RGBI(1) AND NOT RAM_DT(5) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(1) AND NOT RAM_DT(5) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND RAM_DT(5) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND RAM_DT(5) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(5) <= RAM_DT_I(5) when RAM_DT_OE(5) = '1' else 'Z'; RAM_DT_OE(5) <= NOT RAM_WR; FTCPE_RAM_DT6: FTCPE port map (RAM_DT_I(6),RAM_DT_T(6),NOT ZX_CLK,'0','0'); RAM_DT_T(6) <= ((ZX_RGBI(2) AND NOT RAM_DT(6) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(2) AND NOT RAM_DT(6) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND RAM_DT(6) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND RAM_DT(6) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(6) <= RAM_DT_I(6) when RAM_DT_OE(6) = '1' else 'Z'; RAM_DT_OE(6) <= NOT RAM_WR; FTCPE_RAM_DT7: FTCPE port map (RAM_DT_I(7),RAM_DT_T(7),NOT ZX_CLK,'0','0'); RAM_DT_T(7) <= ((ZX_RGBI(3) AND NOT RAM_DT(7) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(3) AND NOT RAM_DT(7) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND RAM_DT(7) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND RAM_DT(7) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(7) <= RAM_DT_I(7) when RAM_DT_OE(7) = '1' else 'Z'; RAM_DT_OE(7) <= NOT RAM_WR; FDCPE_RAM_WR: FDCPE port map (RAM_WR,RAM_WR_D,NOT VGA_CLK,'0','0',NOT vgaDIV); RAM_WR_D <= ((vgaCTCH(1) AND NOT vgaCTCH(0)) OR (zxCTCH(0) AND NOT pWRREQ) OR (zxCTCV(8) AND NOT pWRREQ) OR (NOT pWRREQ AND NOT rWRREQ)); VGA_B <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(6)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(2))); VGA_G <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(5)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(1))); FTCPE_VGA_HS: FTCPE port map (VGA_HS,VGA_HS_T,NOT VGA_CLK,'0','0'); VGA_HS_T <= ((VGA_HS AND vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV) OR (NOT VGA_HS AND vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); VGA_IB <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(6)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(2))); VGA_IG1 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(5)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(1))); VGA_IG2 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(5)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(1))); VGA_IR1 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(4)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(0))); VGA_IR2 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(4)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(0))); VGA_R <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(4)) OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(0))); FTCPE_VGA_VS: FTCPE port map (VGA_VS,VGA_VS_T,NOT VGA_CLK,'0','0',NOT vgaDIV); VGA_VS_T <= ((VGA_VS AND vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND vgaCTCV(1) AND NOT vgaCTCV(2) AND vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9)) OR (NOT VGA_VS AND vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9))); FDCPE_pWRREQ: FDCPE port map (pWRREQ,pWRREQ_D,NOT VGA_CLK,'0','0',NOT vgaDIV); pWRREQ_D <= ((vgaCTCH(1) AND NOT vgaCTCH(0) AND pWRREQ) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT zxCTCH(0) AND NOT zxCTCV(8) AND rWRREQ)); FDCPE_rPIXEL0: FDCPE port map (rPIXEL(0),RAM_DT(0).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(0)); rPIXEL_CE(0) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rPIXEL1: FDCPE port map (rPIXEL(1),RAM_DT(1).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(1)); rPIXEL_CE(1) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rPIXEL2: FDCPE port map (rPIXEL(2),RAM_DT(2).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(2)); rPIXEL_CE(2) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rPIXEL3: FDCPE port map (rPIXEL(3),RAM_DT(3).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(3)); rPIXEL_CE(3) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rPIXEL4: FDCPE port map (rPIXEL(4),RAM_DT(4).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(4)); rPIXEL_CE(4) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rPIXEL5: FDCPE port map (rPIXEL(5),RAM_DT(5).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(5)); rPIXEL_CE(5) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rPIXEL6: FDCPE port map (rPIXEL(6),RAM_DT(6).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(6)); rPIXEL_CE(6) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rPIXEL7: FDCPE port map (rPIXEL(7),RAM_DT(7).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(7)); rPIXEL_CE(7) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); FDCPE_rWRREQ: FDCPE port map (rWRREQ,zxCTCH(0),NOT VGA_CLK,'0','0',NOT vgaDIV); FTCPE_rZXDT40: FTCPE port map (rZXDT4(0),rZXDT4_T(0),NOT ZX_CLK,'0','0'); rZXDT4_T(0) <= ((ZX_RGBI(0) AND NOT zxCTCH(0) AND NOT rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(0) AND NOT zxCTCH(0) AND NOT rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND NOT zxCTCH(0) AND rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND NOT zxCTCH(0) AND rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_rZXDT41: FTCPE port map (rZXDT4(1),rZXDT4_T(1),NOT ZX_CLK,'0','0'); rZXDT4_T(1) <= ((ZX_RGBI(1) AND NOT zxCTCH(0) AND NOT rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(1) AND NOT zxCTCH(0) AND NOT rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND NOT zxCTCH(0) AND rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND NOT zxCTCH(0) AND rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_rZXDT42: FTCPE port map (rZXDT4(2),rZXDT4_T(2),NOT ZX_CLK,'0','0'); rZXDT4_T(2) <= ((ZX_RGBI(2) AND NOT zxCTCH(0) AND NOT rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(2) AND NOT zxCTCH(0) AND NOT rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND NOT zxCTCH(0) AND rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND NOT zxCTCH(0) AND rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_rZXDT43: FTCPE port map (rZXDT4(3),rZXDT4_T(3),NOT ZX_CLK,'0','0'); rZXDT4_T(3) <= ((ZX_RGBI(3) AND NOT zxCTCH(0) AND NOT rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(3) AND NOT zxCTCH(0) AND NOT rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND NOT zxCTCH(0) AND rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND NOT zxCTCH(0) AND rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FDCPE_rZX_CSYC: FDCPE port map (rZX_CSYC,ZX_CSYC,NOT ZX_CLK,'0','0'); FTCPE_vgaCTCH0: FTCPE port map (vgaCTCH(0),vgaCTCH_T(0),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(0) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCH1: FTCPE port map (vgaCTCH(1),vgaCTCH_T(1),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(1) <= ((vgaCTCH(0)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); FTCPE_vgaCTCH2: FTCPE port map (vgaCTCH(2),vgaCTCH_T(2),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(2) <= ((vgaCTCH(1) AND vgaCTCH(0)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); FTCPE_vgaCTCH3: FTCPE port map (vgaCTCH(3),vgaCTCH_T(3),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(3) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(2)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); FTCPE_vgaCTCH4: FTCPE port map (vgaCTCH(4),vgaCTCH_T(4),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(4) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(2) AND vgaCTCH(3)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); FTCPE_vgaCTCH5: FTCPE port map (vgaCTCH(5),vgaCTCH_T(5),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(5) <= (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(2) AND vgaCTCH(3)); FTCPE_vgaCTCH6: FTCPE port map (vgaCTCH(6),vgaCTCH_T(6),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(6) <= (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(2) AND vgaCTCH(3)); FTCPE_vgaCTCH7: FTCPE port map (vgaCTCH(7),vgaCTCH_T(7),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(7) <= (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(2) AND vgaCTCH(3)); FTCPE_vgaCTCH8: FTCPE port map (vgaCTCH(8),vgaCTCH_T(8),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(8) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); FTCPE_vgaCTCH9: FTCPE port map (vgaCTCH(9),vgaCTCH_T(9),NOT VGA_CLK,'0','0',NOT vgaDIV); vgaCTCH_T(9) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); FTCPE_vgaCTCV0: FTCPE port map (vgaCTCV(0),vgaCTCV_T(0),NOT VGA_CLK,'0','0',vgaCTCV_CE(0)); vgaCTCV_T(0) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV); vgaCTCV_CE(0) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV1: FTCPE port map (vgaCTCV(1),vgaCTCV(0),NOT VGA_CLK,'0','0',vgaCTCV_CE(1)); vgaCTCV_CE(1) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV2: FTCPE port map (vgaCTCV(2),vgaCTCV_T(2),NOT VGA_CLK,'0','0',vgaCTCV_CE(2)); vgaCTCV_T(2) <= ((vgaCTCV(1) AND vgaCTCV(0)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV)); vgaCTCV_CE(2) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV3: FTCPE port map (vgaCTCV(3),vgaCTCV_T(3),NOT VGA_CLK,'0','0',vgaCTCV_CE(3)); vgaCTCV_T(3) <= ((vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(0)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV)); vgaCTCV_CE(3) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV4: FTCPE port map (vgaCTCV(4),vgaCTCV_T(4),NOT VGA_CLK,'0','0',vgaCTCV_CE(4)); vgaCTCV_T(4) <= (vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0)); vgaCTCV_CE(4) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV5: FTCPE port map (vgaCTCV(5),vgaCTCV_T(5),NOT VGA_CLK,'0','0',vgaCTCV_CE(5)); vgaCTCV_T(5) <= (vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(5) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV6: FTCPE port map (vgaCTCV(6),vgaCTCV_T(6),NOT VGA_CLK,'0','0',vgaCTCV_CE(6)); vgaCTCV_T(6) <= (vgaCTCV(5) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(6) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV7: FTCPE port map (vgaCTCV(7),vgaCTCV_T(7),NOT VGA_CLK,'0','0',vgaCTCV_CE(7)); vgaCTCV_T(7) <= (vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(7) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV8: FTCPE port map (vgaCTCV(8),vgaCTCV_T(8),NOT VGA_CLK,'0','0',vgaCTCV_CE(8)); vgaCTCV_T(8) <= (vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(8) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaCTCV9: FTCPE port map (vgaCTCV(9),vgaCTCV_T(9),NOT VGA_CLK,'0','0',vgaCTCV_CE(9)); vgaCTCV_T(9) <= ((vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV)); vgaCTCV_CE(9) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); FTCPE_vgaDIV: FTCPE port map (vgaDIV,'1',NOT VGA_CLK,'0','0'); FTCPE_vgaENA: FTCPE port map (vgaENA,vgaENA_T,NOT VGA_CLK,'0','0'); vgaENA_T <= ((vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND vgaCTCH(9) AND vgaENA AND NOT vgaDIV) OR (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND NOT vgaCTCH(9) AND NOT vgaENA AND vgaENv AND NOT vgaDIV)); FTCPE_vgaENv: FTCPE port map (vgaENv,vgaENv_T,NOT VGA_CLK,'0','0',NOT vgaDIV); vgaENv_T <= ((vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND NOT vgaCTCV(1) AND NOT vgaCTCV(2) AND NOT vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9) AND vgaENv) OR (NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND NOT vgaCTCV(1) AND NOT vgaCTCV(2) AND NOT vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9) AND NOT vgaENv)); FDCPE_vgaPAGE: FDCPE port map (vgaPAGE,NOT zxPAGE,NOT VGA_CLK,'0','0',vgaPAGE_CE); vgaPAGE_CE <= (vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9) AND NOT vgaDIV); FTCPE_zxADR0: FTCPE port map (zxADR(0),zxADR_T(0),NOT ZX_CLK,'0','0'); zxADR_T(0) <= ((zxCTCH(0) AND zxCTCH(1) AND NOT zxADR(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND NOT zxADR(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(1) AND zxADR(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(1) AND zxADR(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxADR1: FTCPE port map (zxADR(1),zxADR_T(1),NOT ZX_CLK,'0','0'); zxADR_T(1) <= ((zxCTCH(0) AND zxCTCH(2) AND NOT zxADR(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(2) AND NOT zxADR(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(2) AND zxADR(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(2) AND zxADR(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxADR2: FTCPE port map (zxADR(2),zxADR_T(2),NOT ZX_CLK,'0','0'); zxADR_T(2) <= ((zxCTCH(0) AND zxCTCH(3) AND NOT zxADR(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(3) AND NOT zxADR(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(3) AND zxADR(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(3) AND zxADR(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxADR3: FTCPE port map (zxADR(3),zxADR_T(3),NOT ZX_CLK,'0','0'); zxADR_T(3) <= ((zxCTCH(0) AND zxCTCH(4) AND NOT zxADR(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(4) AND NOT zxADR(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(4) AND zxADR(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(4) AND zxADR(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxADR4: FTCPE port map (zxADR(4),zxADR_T(4),NOT ZX_CLK,'0','0'); zxADR_T(4) <= ((zxCTCH(0) AND zxCTCH(5) AND NOT zxADR(4) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(5) AND NOT zxADR(4) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(5) AND zxADR(4) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(5) AND zxADR(4) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxADR5: FTCPE port map (zxADR(5),zxADR_T(5),NOT ZX_CLK,'0','0'); zxADR_T(5) <= ((zxCTCH(0) AND zxCTCH(6) AND NOT zxADR(5) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(6) AND NOT zxADR(5) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(6) AND zxADR(5) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(6) AND zxADR(5) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxADR6: FTCPE port map (zxADR(6),zxADR_T(6),NOT ZX_CLK,'0','0'); zxADR_T(6) <= ((zxCTCH(0) AND zxCTCH(7) AND NOT zxADR(6) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(7) AND NOT zxADR(6) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(7) AND zxADR(6) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(7) AND zxADR(6) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxADR7: FTCPE port map (zxADR(7),zxADR_T(7),NOT ZX_CLK,'0','0'); zxADR_T(7) <= ((zxCTCH(0) AND zxCTCH(8) AND NOT zxADR(7) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(8) AND NOT zxADR(7) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(8) AND zxADR(7) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(8) AND zxADR(7) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH0: FTCPE port map (zxCTCH(0),zxCTCH_T(0),NOT ZX_CLK,'0','0'); zxCTCH_T(0) <= ((zxCTCH(0) AND NOT ZX_CSYC AND rZX_CSYC) OR (ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH1: FTCPE port map (zxCTCH(1),zxCTCH_T(1),NOT ZX_CLK,'0','0'); zxCTCH_T(1) <= ((zxCTCH(1) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH2: FTCPE port map (zxCTCH(2),zxCTCH_T(2),NOT ZX_CLK,'0','0'); zxCTCH_T(2) <= ((NOT zxCTCH(2) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH3: FTCPE port map (zxCTCH(3),zxCTCH_T(3),NOT ZX_CLK,'0','0'); zxCTCH_T(3) <= ((NOT zxCTCH(3) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH4: FTCPE port map (zxCTCH(4),zxCTCH_T(4),NOT ZX_CLK,'0','0'); zxCTCH_T(4) <= ((NOT zxCTCH(4) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH5: FTCPE port map (zxCTCH(5),zxCTCH_T(5),NOT ZX_CLK,'0','0'); zxCTCH_T(5) <= ((zxCTCH(5) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH6: FTCPE port map (zxCTCH(6),zxCTCH_T(6),NOT ZX_CLK,'0','0'); zxCTCH_T(6) <= ((zxCTCH(6) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH7: FTCPE port map (zxCTCH(7),zxCTCH_T(7),NOT ZX_CLK,'0','0'); zxCTCH_T(7) <= ((NOT zxCTCH(7) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCH8: FTCPE port map (zxCTCH(8),zxCTCH_T(8),NOT ZX_CLK,'0','0'); zxCTCH_T(8) <= ((NOT zxCTCH(8) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND zxCTCH(7) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND zxCTCH(7) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxCTCV0: FTCPE port map (zxCTCV(0),zxCTCV_T(0),NOT ZX_CLK,'0','0'); zxCTCV_T(0) <= ((NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND NOT zxCTCV(0) AND zxCTCH(8) AND NOT rZX_CSYC)); FTCPE_zxCTCV1: FTCPE port map (zxCTCV(1),zxCTCV_T(1),NOT ZX_CLK,'0','0'); zxCTCV_T(1) <= ((zxCTCV(0) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND zxCTCV(1) AND NOT rZX_CSYC)); FTCPE_zxCTCV2: FTCPE port map (zxCTCV(2),zxCTCV_T(2),NOT ZX_CLK,'0','0'); zxCTCV_T(2) <= ((zxCTCV(0) AND zxCTCV(1) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(2) AND NOT rZX_CSYC)); FTCPE_zxCTCV3: FTCPE port map (zxCTCV(3),zxCTCV_T(3),NOT ZX_CLK,'0','0'); zxCTCV_T(3) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(3) AND NOT rZX_CSYC)); FTCPE_zxCTCV4: FTCPE port map (zxCTCV(4),zxCTCV_T(4),NOT ZX_CLK,'0','0'); zxCTCV_T(4) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(4) AND NOT rZX_CSYC)); FTCPE_zxCTCV5: FTCPE port map (zxCTCV(5),zxCTCV_T(5),NOT ZX_CLK,'0','0'); zxCTCV_T(5) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND zxCTCV(5) AND NOT rZX_CSYC)); FTCPE_zxCTCV6: FTCPE port map (zxCTCV(6),zxCTCV_T(6),NOT ZX_CLK,'0','0'); zxCTCV_T(6) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND zxCTCV(5) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(6) AND NOT rZX_CSYC)); FTCPE_zxCTCV7: FTCPE port map (zxCTCV(7),zxCTCV_T(7),NOT ZX_CLK,'0','0'); zxCTCV_T(7) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND zxCTCV(5) AND zxCTCV(6) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(7) AND NOT rZX_CSYC)); FTCPE_zxCTCV8: FTCPE port map (zxCTCV(8),zxCTCV_T(8),NOT ZX_CLK,'0','0'); zxCTCV_T(8) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND zxCTCV(5) AND zxCTCV(6) AND zxCTCV(7) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(8) AND NOT rZX_CSYC)); FTCPE_zxDIV50: FTCPE port map (zxDIV5(0),zxDIV5_T(0),NOT ZX_CLK,'0','0'); zxDIV5_T(0) <= ((NOT ZX_CSYC AND rZX_CSYC AND NOT zxDIV5(0)) OR (NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FDCPE_zxDIV51: FDCPE port map (zxDIV5(1),zxDIV5_D(1),NOT ZX_CLK,'0','0'); zxDIV5_D(1) <= ((NOT ZX_CSYC AND rZX_CSYC) OR (zxDIV5(0) AND zxDIV5(1)) OR (NOT zxDIV5(0) AND NOT zxDIV5(1))); FTCPE_zxDIV52: FTCPE port map (zxDIV5(2),zxDIV5_T(2),NOT ZX_CLK,'0','0'); zxDIV5_T(2) <= ((ZX_CSYC AND zxDIV5(0) AND zxDIV5(1)) OR (NOT ZX_CSYC AND rZX_CSYC AND zxDIV5(2)) OR (NOT rZX_CSYC AND zxDIV5(0) AND zxDIV5(1)) OR (NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); FTCPE_zxPAGE: FTCPE port map (zxPAGE,'1',NOT ZX_CLK,'0','0',zxPAGE_CE); zxPAGE_CE <= (zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND NOT zxCTCV(4) AND zxCTCV(5) AND zxCTCV(6) AND zxCTCV(7) AND NOT zxCTCV(8) AND NOT ZX_CSYC AND rZX_CSYC); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 51 VCC 2 TIE 52 TIE 3 TIE 53 RAM_AD<10> 4 TIE 54 RAM_AD<11> 5 VCC 55 RAM_AD<12> 6 ZX_RGBI<0> 56 RAM_AD<13> 7 ZX_RGBI<1> 57 VCC 8 ZX_RGBI<2> 58 RAM_AD<14> 9 VGA_IR1 59 RAM_AD<15> 10 VGA_IR2 60 RAM_AD<17> 11 VGA_IG1 61 RAM_AD<16> 12 VGA_IG2 62 GND 13 ZX_RGBI<3> 63 RAM_AD<0> 14 ZX_CSYC 64 RAM_AD<1> 15 TIE 65 RAM_AD<2> 16 TIE 66 RAM_AD<3> 17 TIE 67 RAM_AD<4> 18 TIE 68 RAM_WR 19 TIE 69 GND 20 TIE 70 RAM_AD<5> 21 GND 71 RAM_AD<6> 22 VGA_CLK 72 RAM_AD<7> 23 ZX_CLK 73 RAM_AD<8> 24 TIE 74 RAM_AD<9> 25 TIE 75 GND 26 VCC 76 RAM_DT<6> 27 TIE 77 RAM_DT<7> 28 TIE 78 RAM_DT<5> 29 TIE 79 RAM_DT<4> 30 TIE 80 RAM_DT<3> 31 GND 81 RAM_DT<2> 32 VGA_R 82 RAM_DT<1> 33 VGA_G 83 TDO 34 VGA_B 84 GND 35 VGA_IB 85 RAM_DT<0> 36 VGA_HS 86 TIE 37 VGA_VS 87 TIE 38 VCC 88 VCC 39 TIE 89 TIE 40 TIE 90 TIE 41 TIE 91 TIE 42 TIE 92 TIE 43 TIE 93 TIE 44 GND 94 TIE 45 TDI 95 TIE 46 TIE 96 TIE 47 TMS 97 TIE 48 TCK 98 VCC 49 TIE 99 TIE 50 TIE 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : AUTO Ground on Unused IOs : OFF Set I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25