Mouse Port Details Port Meaning #1F(31) Data A #3F(63) Data B #DF mouse button The AMX interface uses a Z80-PIO (programmable In/Out Interface). This chip is fairly complicated, and can operate in several modes. The AMX interface only uses mode 1 (no connection with IM 1 by the way), so this is the only mode that is emulated. The following discussion applies to mode 1 only, and refers to the I/O addresses as used by the AMX mouse interface. The PIO contains two 8-bit interrupt vector registers (VECA and VECB), two 2-bit mode registers (MODEA and MODEB), two 8-bit data registers (DATAA and DATAB), and two 1-bit interrupt-enable latches (IEA and IEB). The data registers can be read at any time through IN ports #1F and #3F respectively. (Note that #1F is also used by the Kempston joystick interface, and also by the Disciple interface, and that #3F is also used by the Multiface.) The other registers cannot be read, only set, through the write-only control register CTRLA and CTRLB, accessed via OUT port #5F and #7F respectively: Bit 7 6 5 4 3 2 1 0 ÚÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ¿ WRITE³ interrupt vector ³ 0 ³ Set interrupt vector ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ Bit 7 6 5 4 3 2 1 0 ÚÄÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ¿ WRITE³ IE ³ x ³ x ³ x ³ 0 ³ x ³ x ³ 1 ³ Set IE latch ÀÄÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ Bit 7 6 5 4 3 2 1 0 ÚÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ¿ WRITE³ MODE ³ x ³ x ³ 1 ³ 1 ³ 1 ³ 1 ³ Set PIO mode ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ If IEA or IEB are set (1), the corresponding interrupt sequences will generate interrupts when prompted by the hardware, and put the corresponding interrupt vector on the data bus at interrupt time. In Z80 Interrupt mode 2, this will then be used as a vector. Note that bit 0 of the vector byte is always 0. Z80 only emulates PIO mode 1 behaviour (bit 7=0, bit 6=1 when setting PIO mode), and won't do anything if the mode is set differently. The AMX interface generates an A interrupt for each 'mickey' the mouse produces in the X direction, and a B interrupt for each mickey in the Y direction. The sign of the direction is stored as a 0 (positive) or 1 (negative) in the respective data registers. One additional port, IN port #DF, reads out the mouse button status. It returns #FF or #00. The AMX is emulated as follows. At every 50 Hz frame, the mouse status is checked, and a PIO interrupt is emulated if necessary. The IRET instruction is trapped, and if caught, more PIO interrupts are emulated if necessary, after actually executing the IRET, with a maximum of 32 interrupts per frame per coordinate. Care is taken to execute the 50 Hz frame interrupt as well. This latter interrupt can be distinguished from PIO interrupts by the fact that it puts a #FF on the bus. It was also necessary to take care of cases where the first instruction executed after a RETI was a HALT, which is then skipped. It seems that the PIO leaves the Z80 in peace for a few clock cycles after seeing a RETI, before generating another interrupt. A reset signal causes the IE latches of the PIO to reset.