DivIDE

DivIDE : ZX Spectrum

DivIDE interface gives 8kB EEPROM, 32kB SRAM, hardware traps and IDE interface. There are firmwares (BIOSes) that reads FAT, simulates +D and D40/D80. They are exclusive and require separate harddisks, as each prefers own structures.

DiwIDE - an upgrade

DiwIDE has some upgrades to original project:

Hardware traps are disabled when ROM0 of ZX Spectrum 128K is paged in. In original project the TR-DOS hardware traps were activated also in 128 BASIC.
More EEPROM - a 32kB chip can be used (28C256). In present v212 only PLCC, what is not compatibile to EEPROM like 29C010.
More SRAM - a 128kB or 512kB SRAM can be used, with battery backup.
A possibility to page 16kB write-enabled RAM. This allows to run other operating systems like CP/M (only on ZX Spectrum 128K due to requiment for extra screen). Also the exit traps (#1FF8..#1FFF) are disabled in this mode.

These all are options. With some small fixes on the board, the DiwIDE can be downgraded to full DivIDE compatibility.

Also, the design is corrected a bit:

Added reset button.
CompactFlash slot as an option to IDE 40pin slot.
Internal ZX Spectrum bus - an upgrade board can be installed inside. For example: Kempston Joystick, AY-3-8910, Z80DMA, Real Time Clock, +D, Interface 1, Interface 2. As an option, memory access can be disabled in this slot, so there are no memory conflicts and firmware only uses I/O ports.
Board enlarged for nice Z-19 case.
PLCC socket for *ROM (are cheaper than DIL).
ZX+3 jumper moved near edge slot.
IDE slot is protected. The harddisk can damage itself when is powered from extral power suppy, while IDE cable on other side is in low impedance ("shorted") by computer being off.

#E3 port upgrade

There are four extra latches at #E3 (227) port. Bit 2 is extra address line for 128kB SRAM (the second is A13). Bits 3 and 4 are extra address lines for 32kB *ROM. Bit 5, when set, forces the 16kB RAM mode - disables the *ROM and write-protected RAM.

Memory map

Original DivIDE memory map
#2000..#3FFF	RAM0	RAM1	RAM2	RAM3
#0000..#1FFF	ROM0	RAM0*

RAM0* is write-protected

DiwIDE 128kB RAM memory map - 8kB ROM + 8kB RAM mode
#2000..#3FFF	RAM0H	RAM1H	RAM2H	RAM3H	RAM4H	RAM5H	RAM6H	RAM7H
#0000..#1FFF	ROM0	ROM1	ROM2	ROM3	RAM0H*

RAM0H* is write protected
the RAM*H is top 8kB of each RAM* 16kB RAM bank

DiwIDE 128kB RAM memory map - 16kB RAM mode
#0000..#1FFF	RAM0	RAM1	RAM2	RAM3	RAM4	RAM5	RAM6	RAM7
#2000..#3FFF	RAM0	RAM1	RAM2	RAM3	RAM4	RAM5	RAM6	RAM7

For 512kB SRAM version, also bits 3 and 4 are used as RAM address lines, so every of 4 ROM banks has own set of 8×8kB RAM banks. In 16kB RAM mode, there are 32 banks of 16kB.

Plans for next releases

Replace the PLCC socket with DIL one to allow also 29*010 like EEPROMs.
Removing the mixing of address lines from EPROM socket.
Allowing the EEPROM to hold also the ZXROM contents.
Both CF and IDE40 support. (CF at bottom of the board, IDE40 slot at top with pins cuted a bit.)
Replacing the 74LS174 with 74LS175 will improve the 8kB RAM mode, for better compatibility.

Files for download

diwi212t.jpg 453.3kB (2006-12-22 23:00): Printed circuit board of DiwIDE v212, top view. The soldermask is over CF mounting pads.
diwi212b.jpg 430.7kB (2006-12-22 23:01): Printed circuit board of DiwIDE v212, bottom view.
diwi-212.zip 83.3kB (2006-11-21 16:31): (old) DiwIDE v212 in Eagle data files. Some things need to be corrected (are in v213).