********** Mapped Logic ********** |
RAM_AD(0) <= ((NOT vgaCTCH(1) AND zxADR(0))
OR (NOT vgaCTCH(0) AND zxADR(0)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(2))); |
RAM_AD(1) <= ((NOT vgaCTCH(1) AND zxADR(1))
OR (NOT vgaCTCH(0) AND zxADR(1)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(3))); |
RAM_AD(2) <= ((NOT vgaCTCH(1) AND zxADR(2))
OR (NOT vgaCTCH(0) AND zxADR(2)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4))); |
RAM_AD(3) <= ((NOT vgaCTCH(1) AND zxADR(3))
OR (NOT vgaCTCH(0) AND zxADR(3)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(5))); |
RAM_AD(4) <= ((NOT vgaCTCH(1) AND zxADR(4))
OR (NOT vgaCTCH(0) AND zxADR(4)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(6))); |
RAM_AD(5) <= ((NOT vgaCTCH(1) AND zxADR(5))
OR (NOT vgaCTCH(0) AND zxADR(5)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(7))); |
RAM_AD(6) <= ((NOT vgaCTCH(1) AND zxADR(6))
OR (NOT vgaCTCH(0) AND zxADR(6)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(8))); |
RAM_AD(7) <= ((NOT vgaCTCH(1) AND zxADR(7))
OR (NOT vgaCTCH(0) AND zxADR(7)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(9))); |
RAM_AD(8) <= ((NOT vgaCTCH(1) AND zxCTCV(0))
OR (NOT vgaCTCH(0) AND zxCTCV(0)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(1))); |
RAM_AD(9) <= ((NOT vgaCTCH(1) AND zxCTCV(1))
OR (NOT vgaCTCH(0) AND zxCTCV(1)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(2))); |
RAM_AD(10) <= ((NOT vgaCTCH(1) AND zxCTCV(2))
OR (NOT vgaCTCH(0) AND zxCTCV(2)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(3))); |
RAM_AD(11) <= ((NOT vgaCTCH(1) AND zxCTCV(3))
OR (NOT vgaCTCH(0) AND zxCTCV(3)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(4))); |
RAM_AD(12) <= ((NOT vgaCTCH(1) AND zxCTCV(4))
OR (NOT vgaCTCH(0) AND zxCTCV(4)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(5))); |
RAM_AD(13) <= ((NOT vgaCTCH(1) AND zxCTCV(5))
OR (NOT vgaCTCH(0) AND zxCTCV(5)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(6))); |
RAM_AD(14) <= ((NOT vgaCTCH(1) AND zxCTCV(6))
OR (NOT vgaCTCH(0) AND zxCTCV(6)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(7))); |
RAM_AD(15) <= ((NOT vgaCTCH(1) AND zxCTCV(7))
OR (NOT vgaCTCH(0) AND zxCTCV(7)) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCV(8))); |
RAM_AD(16) <= ((NOT vgaCTCH(1) AND zxPAGE)
OR (NOT vgaCTCH(0) AND zxPAGE) OR (vgaCTCH(1) AND vgaCTCH(0) AND vgaPAGE)); |
RAM_AD(17) <= '0'; |
FTCPE_RAM_DT0: FTCPE port map (RAM_DT_I(0),RAM_DT_T(0),NOT ZX_CLK,'0','0');
RAM_DT_T(0) <= ((RAM_DT(0) AND zxCTCH(0) AND NOT rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(0) AND zxCTCH(0) AND NOT rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(0) AND zxCTCH(0) AND rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(0) AND zxCTCH(0) AND rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(0) <= RAM_DT_I(0) when RAM_DT_OE(0) = '1' else 'Z'; RAM_DT_OE(0) <= NOT RAM_WR; |
FTCPE_RAM_DT1: FTCPE port map (RAM_DT_I(1),RAM_DT_T(1),NOT ZX_CLK,'0','0');
RAM_DT_T(1) <= ((RAM_DT(1) AND zxCTCH(0) AND NOT rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(1) AND zxCTCH(0) AND NOT rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(1) AND zxCTCH(0) AND rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(1) AND zxCTCH(0) AND rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(1) <= RAM_DT_I(1) when RAM_DT_OE(1) = '1' else 'Z'; RAM_DT_OE(1) <= NOT RAM_WR; |
FTCPE_RAM_DT2: FTCPE port map (RAM_DT_I(2),RAM_DT_T(2),NOT ZX_CLK,'0','0');
RAM_DT_T(2) <= ((RAM_DT(2) AND zxCTCH(0) AND NOT rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(2) AND zxCTCH(0) AND NOT rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(2) AND zxCTCH(0) AND rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(2) AND zxCTCH(0) AND rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(2) <= RAM_DT_I(2) when RAM_DT_OE(2) = '1' else 'Z'; RAM_DT_OE(2) <= NOT RAM_WR; |
FTCPE_RAM_DT3: FTCPE port map (RAM_DT_I(3),RAM_DT_T(3),NOT ZX_CLK,'0','0');
RAM_DT_T(3) <= ((RAM_DT(3) AND zxCTCH(0) AND NOT rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (RAM_DT(3) AND zxCTCH(0) AND NOT rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(3) AND zxCTCH(0) AND rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT RAM_DT(3) AND zxCTCH(0) AND rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(3) <= RAM_DT_I(3) when RAM_DT_OE(3) = '1' else 'Z'; RAM_DT_OE(3) <= NOT RAM_WR; |
FTCPE_RAM_DT4: FTCPE port map (RAM_DT_I(4),RAM_DT_T(4),NOT ZX_CLK,'0','0');
RAM_DT_T(4) <= ((ZX_RGBI(0) AND NOT RAM_DT(4) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(0) AND NOT RAM_DT(4) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND RAM_DT(4) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND RAM_DT(4) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(4) <= RAM_DT_I(4) when RAM_DT_OE(4) = '1' else 'Z'; RAM_DT_OE(4) <= NOT RAM_WR; |
FTCPE_RAM_DT5: FTCPE port map (RAM_DT_I(5),RAM_DT_T(5),NOT ZX_CLK,'0','0');
RAM_DT_T(5) <= ((ZX_RGBI(1) AND NOT RAM_DT(5) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(1) AND NOT RAM_DT(5) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND RAM_DT(5) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND RAM_DT(5) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(5) <= RAM_DT_I(5) when RAM_DT_OE(5) = '1' else 'Z'; RAM_DT_OE(5) <= NOT RAM_WR; |
FTCPE_RAM_DT6: FTCPE port map (RAM_DT_I(6),RAM_DT_T(6),NOT ZX_CLK,'0','0');
RAM_DT_T(6) <= ((ZX_RGBI(2) AND NOT RAM_DT(6) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(2) AND NOT RAM_DT(6) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND RAM_DT(6) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND RAM_DT(6) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(6) <= RAM_DT_I(6) when RAM_DT_OE(6) = '1' else 'Z'; RAM_DT_OE(6) <= NOT RAM_WR; |
FTCPE_RAM_DT7: FTCPE port map (RAM_DT_I(7),RAM_DT_T(7),NOT ZX_CLK,'0','0');
RAM_DT_T(7) <= ((ZX_RGBI(3) AND NOT RAM_DT(7) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(3) AND NOT RAM_DT(7) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND RAM_DT(7) AND zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND RAM_DT(7) AND zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); RAM_DT(7) <= RAM_DT_I(7) when RAM_DT_OE(7) = '1' else 'Z'; RAM_DT_OE(7) <= NOT RAM_WR; |
FDCPE_RAM_WR: FDCPE port map (RAM_WR,RAM_WR_D,NOT VGA_CLK,'0','0',NOT vgaDIV);
RAM_WR_D <= ((vgaCTCH(1) AND NOT vgaCTCH(0)) OR (zxCTCH(0) AND NOT pWRREQ) OR (zxCTCV(8) AND NOT pWRREQ) OR (NOT pWRREQ AND NOT rWRREQ)); |
VGA_B <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(6))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(2))); |
VGA_G <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(5))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(1))); |
FTCPE_VGA_HS: FTCPE port map (VGA_HS,VGA_HS_T,NOT VGA_CLK,'0','0');
VGA_HS_T <= ((VGA_HS AND vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV) OR (NOT VGA_HS AND vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); |
VGA_IB <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(6))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(2))); |
VGA_IG1 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(5))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(1))); |
VGA_IG2 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(5))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(1))); |
VGA_IR1 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(4))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(0))); |
VGA_IR2 <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(7) AND rPIXEL(4))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(3) AND rPIXEL(0))); |
VGA_R <= ((vgaCTCH(1) AND vgaENA AND rPIXEL(4))
OR (NOT vgaCTCH(1) AND vgaENA AND rPIXEL(0))); |
FTCPE_VGA_VS: FTCPE port map (VGA_VS,VGA_VS_T,NOT VGA_CLK,'0','0',NOT vgaDIV);
VGA_VS_T <= ((VGA_VS AND vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND vgaCTCV(1) AND NOT vgaCTCV(2) AND vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9)) OR (NOT VGA_VS AND vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9))); |
FDCPE_pWRREQ: FDCPE port map (pWRREQ,pWRREQ_D,NOT VGA_CLK,'0','0',NOT vgaDIV);
pWRREQ_D <= ((vgaCTCH(1) AND NOT vgaCTCH(0) AND pWRREQ) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT zxCTCH(0) AND NOT zxCTCV(8) AND rWRREQ)); |
FDCPE_rPIXEL0: FDCPE port map (rPIXEL(0),RAM_DT(0).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(0));
rPIXEL_CE(0) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rPIXEL1: FDCPE port map (rPIXEL(1),RAM_DT(1).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(1));
rPIXEL_CE(1) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rPIXEL2: FDCPE port map (rPIXEL(2),RAM_DT(2).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(2));
rPIXEL_CE(2) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rPIXEL3: FDCPE port map (rPIXEL(3),RAM_DT(3).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(3));
rPIXEL_CE(3) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rPIXEL4: FDCPE port map (rPIXEL(4),RAM_DT(4).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(4));
rPIXEL_CE(4) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rPIXEL5: FDCPE port map (rPIXEL(5),RAM_DT(5).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(5));
rPIXEL_CE(5) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rPIXEL6: FDCPE port map (rPIXEL(6),RAM_DT(6).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(6));
rPIXEL_CE(6) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rPIXEL7: FDCPE port map (rPIXEL(7),RAM_DT(7).PIN,NOT VGA_CLK,'0','0',rPIXEL_CE(7));
rPIXEL_CE(7) <= (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaDIV); |
FDCPE_rWRREQ: FDCPE port map (rWRREQ,zxCTCH(0),NOT VGA_CLK,'0','0',NOT vgaDIV); |
FTCPE_rZXDT40: FTCPE port map (rZXDT4(0),rZXDT4_T(0),NOT ZX_CLK,'0','0');
rZXDT4_T(0) <= ((ZX_RGBI(0) AND NOT zxCTCH(0) AND NOT rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(0) AND NOT zxCTCH(0) AND NOT rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND NOT zxCTCH(0) AND rZXDT4(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(0) AND NOT zxCTCH(0) AND rZXDT4(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_rZXDT41: FTCPE port map (rZXDT4(1),rZXDT4_T(1),NOT ZX_CLK,'0','0');
rZXDT4_T(1) <= ((ZX_RGBI(1) AND NOT zxCTCH(0) AND NOT rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(1) AND NOT zxCTCH(0) AND NOT rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND NOT zxCTCH(0) AND rZXDT4(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(1) AND NOT zxCTCH(0) AND rZXDT4(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_rZXDT42: FTCPE port map (rZXDT4(2),rZXDT4_T(2),NOT ZX_CLK,'0','0');
rZXDT4_T(2) <= ((ZX_RGBI(2) AND NOT zxCTCH(0) AND NOT rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(2) AND NOT zxCTCH(0) AND NOT rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND NOT zxCTCH(0) AND rZXDT4(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(2) AND NOT zxCTCH(0) AND rZXDT4(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_rZXDT43: FTCPE port map (rZXDT4(3),rZXDT4_T(3),NOT ZX_CLK,'0','0');
rZXDT4_T(3) <= ((ZX_RGBI(3) AND NOT zxCTCH(0) AND NOT rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (ZX_RGBI(3) AND NOT zxCTCH(0) AND NOT rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND NOT zxCTCH(0) AND rZXDT4(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT ZX_RGBI(3) AND NOT zxCTCH(0) AND rZXDT4(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FDCPE_rZX_CSYC: FDCPE port map (rZX_CSYC,ZX_CSYC,NOT ZX_CLK,'0','0'); |
FTCPE_vgaCTCH0: FTCPE port map (vgaCTCH(0),vgaCTCH_T(0),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(0) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCH1: FTCPE port map (vgaCTCH(1),vgaCTCH_T(1),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(1) <= ((vgaCTCH(0)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); |
FTCPE_vgaCTCH2: FTCPE port map (vgaCTCH(2),vgaCTCH_T(2),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(2) <= ((vgaCTCH(1) AND vgaCTCH(0)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); |
FTCPE_vgaCTCH3: FTCPE port map (vgaCTCH(3),vgaCTCH_T(3),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(3) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(2)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); |
FTCPE_vgaCTCH4: FTCPE port map (vgaCTCH(4),vgaCTCH_T(4),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(4) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(2) AND vgaCTCH(3)) OR (vgaCTCH(1) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); |
FTCPE_vgaCTCH5: FTCPE port map (vgaCTCH(5),vgaCTCH_T(5),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(5) <= (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(2) AND vgaCTCH(3)); |
FTCPE_vgaCTCH6: FTCPE port map (vgaCTCH(6),vgaCTCH_T(6),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(6) <= (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(2) AND vgaCTCH(3)); |
FTCPE_vgaCTCH7: FTCPE port map (vgaCTCH(7),vgaCTCH_T(7),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(7) <= (vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(2) AND vgaCTCH(3)); |
FTCPE_vgaCTCH8: FTCPE port map (vgaCTCH(8),vgaCTCH_T(8),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(8) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); |
FTCPE_vgaCTCH9: FTCPE port map (vgaCTCH(9),vgaCTCH_T(9),NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaCTCH_T(9) <= ((vgaCTCH(1) AND vgaCTCH(0) AND vgaCTCH(4) AND vgaCTCH(5) AND vgaCTCH(6) AND vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV)); |
FTCPE_vgaCTCV0: FTCPE port map (vgaCTCV(0),vgaCTCV_T(0),NOT VGA_CLK,'0','0',vgaCTCV_CE(0));
vgaCTCV_T(0) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV); vgaCTCV_CE(0) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV1: FTCPE port map (vgaCTCV(1),vgaCTCV(0),NOT VGA_CLK,'0','0',vgaCTCV_CE(1));
vgaCTCV_CE(1) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV2: FTCPE port map (vgaCTCV(2),vgaCTCV_T(2),NOT VGA_CLK,'0','0',vgaCTCV_CE(2));
vgaCTCV_T(2) <= ((vgaCTCV(1) AND vgaCTCV(0)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV)); vgaCTCV_CE(2) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV3: FTCPE port map (vgaCTCV(3),vgaCTCV_T(3),NOT VGA_CLK,'0','0',vgaCTCV_CE(3));
vgaCTCV_T(3) <= ((vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(0)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV)); vgaCTCV_CE(3) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV4: FTCPE port map (vgaCTCV(4),vgaCTCV_T(4),NOT VGA_CLK,'0','0',vgaCTCV_CE(4));
vgaCTCV_T(4) <= (vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0)); vgaCTCV_CE(4) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV5: FTCPE port map (vgaCTCV(5),vgaCTCV_T(5),NOT VGA_CLK,'0','0',vgaCTCV_CE(5));
vgaCTCV_T(5) <= (vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(5) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV6: FTCPE port map (vgaCTCV(6),vgaCTCV_T(6),NOT VGA_CLK,'0','0',vgaCTCV_CE(6));
vgaCTCV_T(6) <= (vgaCTCV(5) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(6) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV7: FTCPE port map (vgaCTCV(7),vgaCTCV_T(7),NOT VGA_CLK,'0','0',vgaCTCV_CE(7));
vgaCTCV_T(7) <= (vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(7) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV8: FTCPE port map (vgaCTCV(8),vgaCTCV_T(8),NOT VGA_CLK,'0','0',vgaCTCV_CE(8));
vgaCTCV_T(8) <= (vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)); vgaCTCV_CE(8) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaCTCV9: FTCPE port map (vgaCTCV(9),vgaCTCV_T(9),NOT VGA_CLK,'0','0',vgaCTCV_CE(9));
vgaCTCV_T(9) <= ((vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCV(0) AND vgaCTCV(4)) OR (vgaCTCH(1) AND NOT vgaCTCH(0) AND NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND vgaCTCV(9) AND NOT vgaDIV)); vgaCTCV_CE(9) <= (vgaCTCH(1) AND NOT vgaCTCH(0) AND vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND vgaCTCH(2) AND vgaCTCH(3) AND vgaCTCH(8) AND vgaCTCH(9) AND NOT vgaDIV); |
FTCPE_vgaDIV: FTCPE port map (vgaDIV,'1',NOT VGA_CLK,'0','0'); |
FTCPE_vgaENA: FTCPE port map (vgaENA,vgaENA_T,NOT VGA_CLK,'0','0');
vgaENA_T <= ((vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND vgaCTCH(9) AND vgaENA AND NOT vgaDIV) OR (vgaCTCH(1) AND vgaCTCH(0) AND NOT vgaCTCH(4) AND NOT vgaCTCH(5) AND NOT vgaCTCH(6) AND NOT vgaCTCH(7) AND NOT vgaCTCH(2) AND NOT vgaCTCH(3) AND NOT vgaCTCH(8) AND NOT vgaCTCH(9) AND NOT vgaENA AND vgaENv AND NOT vgaDIV)); |
FTCPE_vgaENv: FTCPE port map (vgaENv,vgaENv_T,NOT VGA_CLK,'0','0',NOT vgaDIV);
vgaENv_T <= ((vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND NOT vgaCTCV(1) AND NOT vgaCTCV(2) AND NOT vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9) AND vgaENv) OR (NOT vgaCTCV(5) AND NOT vgaCTCV(6) AND NOT vgaCTCV(7) AND NOT vgaCTCV(8) AND NOT vgaCTCV(1) AND NOT vgaCTCV(2) AND NOT vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9) AND NOT vgaENv)); |
FDCPE_vgaPAGE: FDCPE port map (vgaPAGE,NOT zxPAGE,NOT VGA_CLK,'0','0',vgaPAGE_CE);
vgaPAGE_CE <= (vgaCTCV(5) AND vgaCTCV(6) AND vgaCTCV(7) AND vgaCTCV(8) AND NOT vgaCTCV(1) AND vgaCTCV(2) AND vgaCTCV(3) AND NOT vgaCTCV(0) AND NOT vgaCTCV(4) AND NOT vgaCTCV(9) AND NOT vgaDIV); |
FTCPE_zxADR0: FTCPE port map (zxADR(0),zxADR_T(0),NOT ZX_CLK,'0','0');
zxADR_T(0) <= ((zxCTCH(0) AND zxCTCH(1) AND NOT zxADR(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND NOT zxADR(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(1) AND zxADR(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(1) AND zxADR(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxADR1: FTCPE port map (zxADR(1),zxADR_T(1),NOT ZX_CLK,'0','0');
zxADR_T(1) <= ((zxCTCH(0) AND zxCTCH(2) AND NOT zxADR(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(2) AND NOT zxADR(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(2) AND zxADR(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(2) AND zxADR(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxADR2: FTCPE port map (zxADR(2),zxADR_T(2),NOT ZX_CLK,'0','0');
zxADR_T(2) <= ((zxCTCH(0) AND zxCTCH(3) AND NOT zxADR(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(3) AND NOT zxADR(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(3) AND zxADR(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(3) AND zxADR(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxADR3: FTCPE port map (zxADR(3),zxADR_T(3),NOT ZX_CLK,'0','0');
zxADR_T(3) <= ((zxCTCH(0) AND zxCTCH(4) AND NOT zxADR(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(4) AND NOT zxADR(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(4) AND zxADR(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(4) AND zxADR(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxADR4: FTCPE port map (zxADR(4),zxADR_T(4),NOT ZX_CLK,'0','0');
zxADR_T(4) <= ((zxCTCH(0) AND zxCTCH(5) AND NOT zxADR(4) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(5) AND NOT zxADR(4) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(5) AND zxADR(4) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(5) AND zxADR(4) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxADR5: FTCPE port map (zxADR(5),zxADR_T(5),NOT ZX_CLK,'0','0');
zxADR_T(5) <= ((zxCTCH(0) AND zxCTCH(6) AND NOT zxADR(5) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(6) AND NOT zxADR(5) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(6) AND zxADR(5) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(6) AND zxADR(5) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxADR6: FTCPE port map (zxADR(6),zxADR_T(6),NOT ZX_CLK,'0','0');
zxADR_T(6) <= ((zxCTCH(0) AND zxCTCH(7) AND NOT zxADR(6) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(7) AND NOT zxADR(6) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(7) AND zxADR(6) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(7) AND zxADR(6) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxADR7: FTCPE port map (zxADR(7),zxADR_T(7),NOT ZX_CLK,'0','0');
zxADR_T(7) <= ((zxCTCH(0) AND zxCTCH(8) AND NOT zxADR(7) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(8) AND NOT zxADR(7) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(8) AND zxADR(7) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT zxCTCH(8) AND zxADR(7) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH0: FTCPE port map (zxCTCH(0),zxCTCH_T(0),NOT ZX_CLK,'0','0');
zxCTCH_T(0) <= ((zxCTCH(0) AND NOT ZX_CSYC AND rZX_CSYC) OR (ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH1: FTCPE port map (zxCTCH(1),zxCTCH_T(1),NOT ZX_CLK,'0','0');
zxCTCH_T(1) <= ((zxCTCH(1) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH2: FTCPE port map (zxCTCH(2),zxCTCH_T(2),NOT ZX_CLK,'0','0');
zxCTCH_T(2) <= ((NOT zxCTCH(2) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH3: FTCPE port map (zxCTCH(3),zxCTCH_T(3),NOT ZX_CLK,'0','0');
zxCTCH_T(3) <= ((NOT zxCTCH(3) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH4: FTCPE port map (zxCTCH(4),zxCTCH_T(4),NOT ZX_CLK,'0','0');
zxCTCH_T(4) <= ((NOT zxCTCH(4) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH5: FTCPE port map (zxCTCH(5),zxCTCH_T(5),NOT ZX_CLK,'0','0');
zxCTCH_T(5) <= ((zxCTCH(5) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH6: FTCPE port map (zxCTCH(6),zxCTCH_T(6),NOT ZX_CLK,'0','0');
zxCTCH_T(6) <= ((zxCTCH(6) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH7: FTCPE port map (zxCTCH(7),zxCTCH_T(7),NOT ZX_CLK,'0','0');
zxCTCH_T(7) <= ((NOT zxCTCH(7) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCH8: FTCPE port map (zxCTCH(8),zxCTCH_T(8),NOT ZX_CLK,'0','0');
zxCTCH_T(8) <= ((NOT zxCTCH(8) AND NOT ZX_CSYC AND rZX_CSYC) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND zxCTCH(7) AND ZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2)) OR (zxCTCH(0) AND zxCTCH(1) AND zxCTCH(2) AND zxCTCH(3) AND zxCTCH(4) AND zxCTCH(5) AND zxCTCH(6) AND zxCTCH(7) AND NOT rZX_CSYC AND NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxCTCV0: FTCPE port map (zxCTCV(0),zxCTCV_T(0),NOT ZX_CLK,'0','0');
zxCTCV_T(0) <= ((NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND NOT zxCTCV(0) AND zxCTCH(8) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV1: FTCPE port map (zxCTCV(1),zxCTCV_T(1),NOT ZX_CLK,'0','0');
zxCTCV_T(1) <= ((zxCTCV(0) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND zxCTCV(1) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV2: FTCPE port map (zxCTCV(2),zxCTCV_T(2),NOT ZX_CLK,'0','0');
zxCTCV_T(2) <= ((zxCTCV(0) AND zxCTCV(1) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(2) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV3: FTCPE port map (zxCTCV(3),zxCTCV_T(3),NOT ZX_CLK,'0','0');
zxCTCV_T(3) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(3) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV4: FTCPE port map (zxCTCV(4),zxCTCV_T(4),NOT ZX_CLK,'0','0');
zxCTCV_T(4) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(4) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV5: FTCPE port map (zxCTCV(5),zxCTCV_T(5),NOT ZX_CLK,'0','0');
zxCTCV_T(5) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND zxCTCV(5) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV6: FTCPE port map (zxCTCV(6),zxCTCV_T(6),NOT ZX_CLK,'0','0');
zxCTCV_T(6) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND zxCTCV(5) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(6) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV7: FTCPE port map (zxCTCV(7),zxCTCV_T(7),NOT ZX_CLK,'0','0');
zxCTCV_T(7) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND zxCTCV(5) AND zxCTCV(6) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(7) AND NOT rZX_CSYC)); |
FTCPE_zxCTCV8: FTCPE port map (zxCTCV(8),zxCTCV_T(8),NOT ZX_CLK,'0','0');
zxCTCV_T(8) <= ((zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND zxCTCV(4) AND zxCTCV(5) AND zxCTCV(6) AND zxCTCV(7) AND NOT ZX_CSYC AND rZX_CSYC) OR (NOT zxCTCH(0) AND NOT zxCTCH(1) AND NOT zxCTCH(2) AND NOT zxCTCH(3) AND NOT zxCTCH(4) AND NOT zxCTCH(5) AND NOT zxCTCH(6) AND NOT zxCTCH(7) AND zxCTCH(8) AND NOT zxCTCV(8) AND NOT rZX_CSYC)); |
FTCPE_zxDIV50: FTCPE port map (zxDIV5(0),zxDIV5_T(0),NOT ZX_CLK,'0','0');
zxDIV5_T(0) <= ((NOT ZX_CSYC AND rZX_CSYC AND NOT zxDIV5(0)) OR (NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FDCPE_zxDIV51: FDCPE port map (zxDIV5(1),zxDIV5_D(1),NOT ZX_CLK,'0','0');
zxDIV5_D(1) <= ((NOT ZX_CSYC AND rZX_CSYC) OR (zxDIV5(0) AND zxDIV5(1)) OR (NOT zxDIV5(0) AND NOT zxDIV5(1))); |
FTCPE_zxDIV52: FTCPE port map (zxDIV5(2),zxDIV5_T(2),NOT ZX_CLK,'0','0');
zxDIV5_T(2) <= ((ZX_CSYC AND zxDIV5(0) AND zxDIV5(1)) OR (NOT ZX_CSYC AND rZX_CSYC AND zxDIV5(2)) OR (NOT rZX_CSYC AND zxDIV5(0) AND zxDIV5(1)) OR (NOT zxDIV5(0) AND NOT zxDIV5(1) AND zxDIV5(2))); |
FTCPE_zxPAGE: FTCPE port map (zxPAGE,'1',NOT ZX_CLK,'0','0',zxPAGE_CE);
zxPAGE_CE <= (zxCTCV(0) AND zxCTCV(1) AND zxCTCV(2) AND zxCTCV(3) AND NOT zxCTCV(4) AND zxCTCV(5) AND zxCTCV(6) AND zxCTCV(7) AND NOT zxCTCV(8) AND NOT ZX_CSYC AND rZX_CSYC); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |